1. Field of the Invention
The present technology relates to digital circuits and more particularly to output buffers of digital circuits.
2. Description of Related Art
An output buffer in an integrated circuit may be used to receive internal data at low current levels and present it to external loading at higher current levels. The output timing of the output buffer may vary with process corners, voltages, and temperatures (PVT). Variations in output timing due to PVT conditions may reduce the data valid window. The higher the operating speed, the more likely the reduced data valid window may affect the performance and even the reliability of the integrated circuit.
One known output buffer is described in U.S. Pat. No. 8,643,404, directed to “Self-Calibration of Output Buffer Driving Strength”. In the '404 Patent, the output driving strength is changed iteratively, where the result of any iterative change results in either a “stronger” or “weaker” driving strength. If the initial driving strength is far off, then reaching the ideal driving strength may require multiple iterations.
It is desirable to provide an output buffer that is substantially insensitive to PVT conditions and thus provide reliable performance for high speed operations of integrated circuits, and have good results for consistent output buffer timing delay, with a less iterative approach to reaching an ideal output buffer timing delay.